Magnetoresistive devices and methods of fabricating such devices

ABSTRACT

An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.

TECHNICAL FIELD

The present disclosure relates generally to magnetoresistive devices andmethods of fabricating magnetoresistive devices.

INTRODUCTION

Magnetoresistive devices, such as magnetic sensors, magnetictransducers, and magnetic memory cells, include magnetic materials wherethe magnetic moments of those materials can be varied to provide sensinginformation or store data. Magnetoresistive devices, spin electronicdevices, and spintronic devices are synonymous terms for devices thatmake use of effects predominantly caused by electron spin.Magnetoresistive memory devices are used in numerous information devicesto provide non-volatile, reliable, radiation resistant, and high-densitydata storage and retrieval. The numerous magnetoresistive devices mayinclude, but are not limited to, Magnetoresistive Random Access Memory(MRAM), magnetic sensors, and read/write heads for disk drives.

Manufacturing magnetoresistive devices includes a sequence of processingsteps wherein multiple layers of materials are deposited and patternedto form a magnetoresistive stack and the electrodes used to provideelectrical connections to the magnetoresistive stack. Themagnetoresistive stack includes the various regions or layers that makeup “free” and “fixed” portions of the device as well as one or moreintermediate regions (e.g., dielectric layers) that separate these“free” and “fixed” portions, and in some cases, provide at least onetunnel junction for the device. In many instances, the layers ofmaterial in the magnetoresistive stack may be relatively very thin,e.g., on the order of a few or tens of angstroms. The term “free” refersto ferromagnetic regions having a magnetic moment that may shift or movesignificantly in response to applied magnetic fields or spin-polarizedcurrents used to switch the magnetic moment vector of a “free” region.And, the term “fixed” refers to ferromagnetic regions having a magneticmoment vector does not move substantially in response to such appliedmagnetic fields or spin-polarized currents.

In some applications, magnetoresistive devices may be included on thesame integrated circuit with additional surrounding circuitry. Forexample, magnetoresistive devices (MRAMS, magnetic sensors, magnetictransducers, etc.) may be included on an integrated circuit with amicrocontroller or other processing circuitry configured to utilize theinformation collected by, or stored in, the magnetoresistive devices.Aspects of this disclosure describe magnetoresistive devices andtechniques for fabricating integrated circuits that includemagnetoresistive devices that allow for efficient integration withrespect to established integrated circuit manufacturing process flows.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present disclosure may be implemented in connectionwith aspects illustrated in the attached drawings. These drawings showdifferent aspects of the present disclosure and, where appropriate,reference numerals illustrating like structures, components, materials,and/or elements in different figures are labeled similarly. It isunderstood that various combinations of the structures, components,and/or elements, other than those specifically shown, are contemplatedand are within the scope of the present disclosure.

For simplicity and clarity of illustration, the figures depict thegeneral structure and/or manner of construction of the variousembodiments/aspects described herein. Further, the figures depict thedifferent layers/regions of the illustrated stacks as having a uniformthickness and well-defined boundaries with straight edges. However, aperson skilled in the art would recognize that, in reality, thedifferent layers typically may have a non-uniform thickness. And, at theinterface between adjacent layers, the materials of these layers mayalloy together, or migrate into one or the other material, making theirboundaries ill-defined. Descriptions and details of well-known features(e.g., interconnects, etc.) and techniques may be omitted to avoidobscuring other features. Elements in the figures are not necessarilydrawn to scale. The dimensions of some features may be exaggeratedrelative to other features to improve understanding of the exemplaryembodiments. Cross-sectional views are simplifications provided to helpillustrate the relative positioning of various regions/layers anddescribe various processing steps. One skilled in the art wouldappreciate that the cross-sectional views are not drawn to scale andshould not be viewed as representing proportional relationships betweendifferent regions/layers. Moreover, while certain features areillustrated with straight 90-degree edges, in reality such features maybe more “rounded” and/or gradually sloping or tapered.

Further, one skilled in the art would understand that, although multiplelayers with distinct interfaces are illustrated in the figures, in somecases, over time and/or exposure to high temperatures, materials of someof the layers may migrate into or interact with materials of otherlayers to present a more diffuse interface between these layers. Itshould be noted that, even if it is not specifically mentioned, aspectsdescribed with reference to one embodiment may also be applicable to,and may be used with, other embodiments.

FIG. 1 is an illustration of the top view of an exemplary integratedcircuit (IC) device of the current disclosure;

FIGS. 2A and 2B are cross-sectional illustrations of known IC deviceswith magnetoresistive devices;

FIG. 3 is a cross-sectional illustration of the disclosed IC device ofFIG. 1;

FIGS. 4A-4I are schematic illustrations of the IC device of FIG. 3 atdifferent stages of an exemplary fabrication process;

FIGS. 5A-5H are schematic illustrations of the IC device of FIG. 3 atdifferent stages of another exemplary fabrication process;

FIG. 6 illustrates an exemplary fabrication process of the IC device ofFIG. 3;

FIG. 7 is a schematic diagram of an exemplary magnetoresistive memorystack electrically connected to a select device, e.g., an accesstransistor, in a magnetoresistive memory cell configuration;

FIGS. 8A and 8B are schematic block diagrams of integrated circuitsincluding a discrete memory device and an embedded memory device,respectively, each including an MRAM (which, in one embodiment isrepresentative of one or more arrays of MRAM having a plurality ofmagnetoresistive memory stacks according to aspects of certainembodiments of the present disclosure); and

FIGS. 9A-9D are cross-sectional illustrations of an exemplarymagnetoresistive device of the IC device of FIG. 3.

DETAILED DESCRIPTION

There are many embodiments described and illustrated herein. The presentdisclosure is neither limited to any single aspect nor embodimentthereof, nor to any combinations and/or permutations of such aspectsand/or embodiments. Moreover, each aspect of the present disclosure,and/or embodiments thereof, may be employed alone or in combination withone or more of the other aspects of the present disclosure and/orembodiments thereof. For the sake of brevity, certain permutations andcombinations are not discussed and/or illustrated separately herein.Notably, an embodiment or implementation described herein as “exemplary”is not to be construed as preferred or advantageous, for example, overother embodiments or implementations; rather, it is intended reflect orindicate that the embodiment(s) is/are “example” embodiment(s). Further,even though the figures and this written disclosure appear to describe aparticular order of construction (e.g., from bottom to top), it isunderstood that the depicted structures may have the opposite order(e.g., from top to bottom), or a different order.

For the sake of brevity, conventional techniques related tosemiconductor processing may not be described in detail herein. Theexemplary embodiments described herein may be fabricated using knownlithographic processes. The fabrication of integrated circuits,microelectronic devices, micro electro mechanical devices, microfluidicdevices, and photonic devices may involve the creation of several layersof materials that interact in some fashion. One or more of these layersmay be patterned so various regions of the layer have differentelectrical or other characteristics, which may be interconnected withinthe layer or to other layers to create electrical components andcircuits. These regions may be created by selectively introducing orremoving various materials. The patterns that define such regions areoften created by lithographic processes. For example, a layer ofphotoresist may be applied onto a layer overlying a wafer substrate. Aphoto mask (containing clear and opaque areas) is used to selectivelyexpose the photoresist by a form of radiation, such as ultravioletlight, electrons, or x-rays. Either the photoresist exposed to theradiation, or that is not exposed to the radiation, is removed by theapplication of a developer. An etch may then be applied to theunderlying layer not protected by the remaining photoresist such thatthe layer overlying the substrate is patterned. Alternatively, anadditive process can be used in which a structure is built up using thephotoresist as a template.

There are many inventions described and illustrated herein, as well asmany aspects and embodiments of those inventions. In one aspect, thedescribed embodiments relate to, among other things, methods ofmanufacturing integrated circuits that include magnetoresistive deviceshaving electrically conductive electrodes on either side of a magneticmaterial stack. While not described in detail herein, the magneticmaterial stack may include many different layers of material, where someof the layers include magnetic materials, whereas others do not. In someembodiments, the methods of manufacturing include forming the layers ofthe magnetoresistive devices and then masking and etching those layersto produce the magnetoresistive device. Examples of such devices includetransducers such as electromagnetic sensors as well as memory cells.

Magnetoresistive devices can be included on an integrated circuit withother circuitry. In such cases, it is desirable to align the processsteps and structures associated with the magnetoresistive devices withthe process steps and circuit features associated with the surroundingcircuitry. In other words, integrating the manufacture of themagnetoresistive devices into the standard process flow used tomanufacture the integrated circuits may be desirably performed in amanner that minimizes the number of additional processing steps andmaterials needed during production. For example, while some processsteps and materials associated with building magnetoresistive devicesmay be specific to such devices, other process steps and materials usedin manufacturing magnetoresistive devices also may be used inmanufacturing the surrounding circuitry. As a specific example,conductive layers that are deposited and patterned to form the topand/or bottom electrodes for magnetoresistive devices can also be usedto form connective traces and interlayer connections in standardcomplementary metal oxide semiconductor (CMOS) process flows. As anadditional example, embodiments are disclosed in which the interlayerdielectric used in the portion of the integrated circuit that includesmagnetoresistive devices is the same standard-process-flow interlayerdielectric used in the remainder of the integrated circuit. Such reuseeliminates the need for additional magnetoresistive-device-specificprocessing and materials.

Unless defined otherwise, all terms of art, notations and otherscientific terms or terminology used herein have the same meaning as iscommonly understood by one of ordinary skill in the art to which thisdisclosure belongs. Some of the components, structures, and/or processesdescribed or referenced herein are well understood and commonly employedusing conventional methodology by those skilled in the art. Therefore,these components, structures, and processes will not be described indetail. All patents, applications, published applications and otherpublications referred to herein are incorporated by reference in theirentirety. If a definition or description set forth in this disclosure iscontrary to, or otherwise inconsistent with, a definition and/ordescription in these references, the definition and/or description setforth in this disclosure prevails over those in the references that areincorporated herein by reference. None of the references described orreferenced herein is admitted to be prior art to the current disclosure.

FIG. 1 illustrates an exemplary integrated circuit (IC) device 100 thatincludes a logic portion 110 and a magnetoresistive device portion 120.Logic portion 110 may include logic circuits and other circuitstypically manufactured using conventional process flows. Themagnetoresistive device portion 120 may include magnetoresistive devicessuch as, for example, magnetic memory devices (MRAMs), magnetic sensors,magnetic transducers, etc. For brevity, the magnetoresistive deviceportion 120 is hereinafter referred to as the memory portion 120. Memoryportion 120 may include any suitable configuration and number ofmagnetoresistive devices, and the logic portion 110 may include logiccircuit elements. Although not shown in FIG. 1, in some cases, IC device100 may include a buffer portion between logic portion 110 and memoryportion 120. The buffer portion may include, e.g., “dummy”magnetoresistive devices that are not intended for active operation.Instead, such “dummy” magnetoresistive devices may be used to facilitateprocessing of IC device 100. For example, in some cases, polishing of ICdevice 100 may result in “dishing,” where an uneven surface results dueto the abrupt change from a high density of magnetoresistive devices inportion 120 to a lack of such devices in portion 110. To alleviate suchissues, in some embodiments, the buffer portion between logic andmagnetic portions 110, 120 may include “dummy” magnetoresistive devicespatterned or tiled to maintain a desired density of magnetoresistivedevices between portions 110 and 120. Additionally or alternatively, insome embodiments, other structures designed to facilitate processing maybe provided in the buffer portion.

In IC device 100, the magnetoresistive devices and logic circuits may beintercoupled using metal layers (referred to M1, M2, M3, . . . Mxlayers) and via layers (V1, V2, V3, etc.). As would be known to a personof ordinary skill in the art, the individual circuit components (e.g.,transistors, capacitors, diodes, etc.) of IC device 100 are fabricatedon a semiconductor wafer. These circuit components are then connected toeach other to distribute signals, as well as power and ground. Sincethere is no room on the wafer surface to create all the requiredconnections in a single layer, these connections are typically createdin multiple vertically stacked levels of interconnects (i.e., metallayers M1, M2, etc.). Each metal layer usually includes interconnects(e.g., elongate interconnects) that extend in an in-plane direction(i.e., in the XY plane in FIG. 1). The multiple metal layers, and theinterconnects of each metal layer, are separated from each other by oneor more dielectric materials (i.e., interlayer dielectrics) thatelectrically isolate the different metal layers (M1, M2, etc.). Vias(V1, V2, etc.) between the different metal layers provide electricalconnection between the different metal layers. For example, vias thatconnect metal features (or metallizations) in the M1 layer to thefeatures in the M2 layer are called V1 vias, and vias that connectfeatures in the M2 layer to features in the M3 layer are called V2 vias.Typically, a via is a relatively small opening on the interlayerdielectric between two metal layers that is filled with an electricallyconductive material that provides electrical connectivity between twoadjacent metal layers. As is also known to a person of ordinary skill inthe art, lower-level metal layers (i.e., metal layers close to thetransistors or other circuit components of IC device 100) are usuallysmaller than higher-level metal layers because, for example, theselower-level metal layer features attach to components that arethemselves very small and often closely packed together. Theselower-level metal layers—called local interconnects—are usually thin andshort in length as compared to the higher-level metal layers—calledglobal interconnects—that are typically thicker and longer. While asimple IC device may have just a few levels of metal layers (e.g., 2-4,etc.), a more complex IC device may have may many more levels of metallayers (e.g., 5-10, etc.).

IC device 100 may, without limitation, have any suitable number of metallayers. Although the specific embodiments presented below describe an ICdevice with a particular number of metal layers, this is only exemplary.Other embodiments may include a greater or lesser number of metallayers. As explained above, the multiple layers of metal are verticallyspaced-apart from each other and separated by an interlayer dielectric(ILD) layer. In order to provide electrical coupling between thesemultiple metal layers, vias are formed through the ILD that separatesadjacent metal layers. In general, as explained above, via layer VXelectrically connects metal layers MX and MX+1, etc. In some aspects,ILD may surround and insulate the vias and/or interconnect wiring of ICdevice 100.

In FIGS. 2A and 2B, cross-sectional views of a portion of a known ICdevice 100′ is presented to illustrate an exemplary structure of logicand magnetic portions 110, 120 in known devices 100′. A cross-sectionalview of the corresponding region in an embodiment of the disclosed ICdevice 100 will then be presented in FIG. 3 to illustrate some of thedifferences between a known IC device 100′ and the disclosed IC device100. In FIGS. 2A, 2B and 3, the two column-like vertical structures onthe right side illustrate the circuitry associated with exemplarymagnetoresistive devices 210 (MTJ device 210) of memory portion 120, andthe two vertical structures on the left side illustrate exemplary logiccircuits in logic portion 110. Although only two MTJ 210 are illustratedin the memory portion 120 of these figures, a person of ordinary skillin the art would recognize that, in reality, memory portion 120typically includes many (e.g., hundreds, thousands, or any number) MTJdevices 210 spaced apart from each other (e.g., in both X and Ydirections).

With specific reference to logic portion 110 of FIGS. 2A and 2B, thelabels M1, M2, and M3 correspond to the first three metal layers of ICdevice 100′, with layer M1 closer to the transistors (or other CMOScircuitry) formed on substrate 300 of device 100′ than metal layer M3.And, the label V1 corresponds to the via layer between (i.e., thatelectrically connects) metal layers M1 and M2, and the label V2corresponds to the via layer between metal layers M2 and M3. Asillustrated in FIGS. 2A and 2B, in the logic portion 110, a feature 154(e.g. trace, pad, or other connection point) in metal layer M1 iselectrically connected to a feature 154 in the metal layer M2 (trace,pad, etc.) through via 152 in via layer V1. Similarly, a feature 154 inthe metal layer M2 is electrically connected to feature 154 in the metallayer M3 using a via 152 in via layer V2. In some embodiments, features154 and vias 152 may have a substantially circular cross-sectionalshape. However, this is not a limitation. These structures may, ingeneral, have any cross-sectional shape (square, rectangular, etc.).

It should be noted that the features 154 and the vias 152 of thedifferent metal layers and via layers are shown as having a similar size(width/diameter, thickness, etc.) and configuration only for the sake ofsimplicity. As previously explained, typically, the features of thelower-level metal layers (i.e., closer to substrate 300, e.g., M1) willbe substantially smaller than those in the higher-level metal layers(i.e., further away from substrate 300, e.g., M3). The illustratedrelative dimensions of the metal and via layers are also exemplary. Insome embodiments, the height of a via layer may be only about ½ to ⅔ theheight of an adjacent metal layer. The space between the different metaland via layers in both the logic and memory portions 110, 120 are filledwith ILD 300.

With continuing reference to FIGS. 2A and 2B, the memory portion 210includes a plurality of MTJ devices 210 embedded therein. As is known toa person of ordinary skill in the art, MTJ device 210 includes amagnetoresistive stack 250 with a plurality of magnetic material layers(or regions) separated by one or more intermediate layers. In someembodiments, these intermediate layers may be made of a dielectricmaterial and may form one or more tunnel junctions. For example, in someembodiments, magnetoresistive stack 250 may include dielectric layersandwiched between one or more magnetic material layers on one side(that form a magnetically “free” region of MTJ device 210) and one ormore magnetic material layers on the opposite side (that form amagnetically “fixed” region of MTJ device 210) to form a magnetic tunneljunction. MTJ device 210 may also include a bottom electrode 240 and atop electrode 260. Bottom and top electrodes 240, 260 may be formed ofany electrically conductive material that enables the magnetoresistivestack 250 to be accessed by surrounding circuitry. In some examples, theinsulating dielectric layer may be replaced with a conductive layer(e.g., a copper layer) sandwiched between the “free” and “fixed”regions.

In some known IC devices 100′, an MTJ device 210 is incorporated betweentwo alternate metal layers, such as, for example, between metal layers(M1 and M3 as illustrated in FIG. 2A, M2 and M3 as illustrated in FIG.2B). To integrate the MTJ device 210 in the space between the two metallayers (e.g., M1 and M3), a reduced-height custom via, called a magneticvia (or Mvia 230) is fabricated to couple the bottom electrode 240 ofMTJ device 210 to feature 154 of the metal layer below (i.e., M1 layerin FIG. 2A). As illustrated in FIG. 2A, the Mvias 230 that connect MTJdevices 210 to the metal layer below have a different configuration thatvias 152 of the logic portion 110 in the V1 layer. For example, in someembodiments, Mvias 230 of the memory portion 120 have a relativelylarger width or diameter than vias 152 in the logic portion 110. Mvias230 with a larger width may provide landing tolerance for MTJ devices210 that will be formed thereon. Although not illustrated in FIG. 2A, insome embodiments, Mvias 230 may have a larger width or diameter than thefeatures 154 that it lands on to provide landing tolerance. Since Mvias230 of the memory portion 120 and vias 152 of the logic portion 110 inthe V1 layer have a different configuration, these vias (152 and 230)have to be formed using different processing steps, thereby increasingfabrication complexity and associated costs. A via 152 (sometimes calleda tunnel junction via or a TJvia) couples the top electrode 260 of MTJdevice 210 to a feature 154 of the metal layer above (M3 layer in FIG.2A). See, for example, commonly-assigned U.S. Pat. Nos. 8,790,935 B1 and9,711,566 B1 which are incorporated by reference in their entireties. Ascan be seen in FIG. 2A, TJVias 152 that couple MTJ devices 210 tofeatures 154 of the M3 layer have a similar (or the same) configurationas vias 152 of the V2 layer in the logic portion 110 of IC device 100′.Since all the vias 152 in the V2 layer have a similar configuration,they may be formed using a common set of processing steps, duringfabrication of device 100′. In some known IC devices 100′ (e.g., intypical conventional IC devices), as illustrated in FIG. 2B, the entireMVia 230, MTJ device 210, and TJVia 152′ is contained within the heightof a via, such as the height of via 152 in the V2 layer, if the V2 layervia is replaced.

Note that, in IC device 100′ of FIG. 2A, MTJ device 210 (i.e., bottomelectrode 240, magnetoresistive stack 250, and top electrode 260) alongwith the customized via (i.e., Mvia 230) formed to couple MTJ device 210to the metal layer below is fit in (or integrated in) the space (e.g.,height) occupied by a metal and a via layer of the logic portion 110.That is, as illustrated in FIG. 2A, the combined height of all thelayers associated with MTJ device 210 (i.e., height of Mvia 230+bottomelectrode 240+magnetoresistive stack 250+top electrode 260) issubstantially equal to the combined height 270 of via layer V1 and metallayer M2 (V1+M2). See, for example, commonly-assigned U.S. Pat. No.9,412,786, which is incorporated by reference in its entirety herein. Asa person or ordinary skill in the art would recognize, the absolutevalue of height 270 depends upon the specific metal layers between whichthe MTJ devices 210 are embedded (i.e., between M1 and M3, between M3and M5, etc.) and the foundry-dependent design rules for the technologynode (circuit generation, architecture, etc.) corresponding to the ICdevice. And, in the IC device 100′ illustrated in FIG. 2B, the combinedheight of MVia 230+MTJ device 210+TJ Via 152′ is substantially equal tothe height of the V2 via layer.

As would be recognized by a person of ordinary skill in the art, designrules specify the geometric and connectivity restrictions (includingheight, width, etc.) in an IC device to ensure sufficient manufacturingyield while accounting for the variabilities in the fabricationprocesses used to fabricate the device. In some technology nodes, designrules may require height 270 of FIG. 2A to be about 180 nm. In suchcases, the height of magnetoresistive stack 250 may be about 21 nm, theheight of bottom electrode 230 may be about 25 nm, the height of topelectrode 260 may be 60 nm, and the height of Mvia may be about 74 nm.Thus, in FIG. 2A, the combined height of bottom electrode 230,magnetoresistive stack 250, top electrode 260, and Mvia 230 is about 180nm (25+21+60+74), which is the same as the combined height 270 of the M2and V1 layers.

As explained with reference to FIGS. 2A and 2B, in known IC devices, MTJdevices 210 are incorporated (or integrated) in the space occupied by ametal layer and a via layer (i.e., V1+M2 layer in FIG. 2A, or moregenerally, VX layer+MX+1 layer, where X can be any layer), or in thespace occupied by a via layer (such as, the V2 layer as illustrated inFIG. 2B or in any other via layer). In embodiments of the currentdisclosure, rather than integrating MTJ devices 210 in the spaceoccupied by a metal layer and a via layer (as in FIG. 2A), orintegrating MTJ devices 210 in the space occupied by a via layer (as inFIG. 2B), the MTJ devices 210 are integrated in a metal layer (i.e.,with reference to FIG. 3, in MX+1 layer rather than VX+MX+1 layer). Aswill be explained layer, integrating MTJ devices only in a metal layermay advantageously result in die size reduction and reduce thepossibility of electrical shorts in device 100. FIG. 3 is across-sectional view of a portion of IC device 100 of FIG. 1 that showsexemplary MTJ devices 210 integrated in a metal layer MX+1. As explainedabove, metal layer MX+1 may be any metal layer of device 100. That is,if IC device 100 has 8 metal layers (M1 to M8), metal layer MX+1 may beany metal layer from M1 to M8. Since the configuration of MTJ devices210 and other circuit elements (e.g., features 152, vias, 152, etc.) ofIC device 100 of FIG. 3 are the substantially similar to those in ICdevice 100′ of FIGS. 2A and 2B, they are not described again withreference to FIG. 3.

As illustrated in FIG. 3, MTJ devices 210 are integrated solely in metallayer MX+1 of IC device 100. That is, the height of MTJ device 210(i.e., the height of bottom electrode 240+magnetoresistive stack 250+topelectrode 260) is substantially equal to the height of the MX+1 layer.Since the MTJ devices 210 have similar height as the features of a metallayer, the Mvias 230 (see FIG. 2A) that connect MTJ devices 210 to themetal layer below (i.e., MX layer in FIG. 3) is eliminated in IC device100, and vias similar in configuration to vias 152 in the logic portion110 (of the same via layer) is used to connect MTJ devices 210 to themetal layer below. That is, as illustrated in FIG. 3, vias 152 thatconnect the bottom electrodes 240 of MTJ devices 210 to features 154 ofthe MX layer is similar in configuration (e.g., size, etc.) to othervias 152 of the VX layer. That is, as illustrated in FIG. 3, in ICdevice 100, all the circuit elements associated with MTJ device 210(i.e., bottom electrode 240, magnetoresistive stack 250, and topelectrode 260) is fit into (or integrated in) the space (e.g., height)occupied by only metal layer MX+1. Compared with a known IC device 100′of FIG. 2A, in the embodiment of FIG. 3, the Mvia 230 of FIG. 2A isreplaced with a via 152 that has a similar (or the same) configurationas the corresponding vias 152 in the logic portion 110. Therefore, insome embodiments, vias 152 of both the logic and memory portions 110,120 may be formed using similar processing steps, thereby simplifyingfabrication.

Although the configuration of both MTJ devices 210 of FIG. 3 are shownto be identical, this is only exemplary. In some cases, there may bevariations between the different MTJ devices 210 embedded in memoryportion 120. Although in some cases, the differences in configurationcan be intentional (e.g., MTJ devices 210 designed to be different),typically, the differences in configuration between different MTJdevices 210 in memory portion 120 occur as a result of variations duringprocessing (e.g., deposition, etching, etc.). For example, variationsduring deposition and/or etching may cause differences in the heights ofthe top electrodes 260 (and/or other components) in different MTJdevices 210. Because of such variations, the height of MTJ devices 210may not necessarily be exactly the same as the height of features 154 ofMX+1 layer (which may also vary across the device 100). Instead, inembodiments of the current disclosure, the average height of MTJ devices210 (i.e., combined height of bottom electrode 240, magnetoresistivestack 250, and top electrode 260) in memory portion 120 may besubstantially the same as the average height of features 154 of metallayer MX+1 in the logic portion 110. In other words, MTJ devices 210(i.e., bottom electrode 240, magnetoresistive stack 250, and topelectrode 260) of memory portion 120 may substantially fit into thespace (e.g., height) occupied by metal layer MX+1.

As illustrated in FIG. 3, ILD 300 may fill the space between the metalfeatures of IC device 100. ILD 300 may include a conventional ILDmaterial (such as, for example, TEOS, SiO₂, etc.) or a low-k ILDmaterial (such as, for example, carbon doped SiO₂ (SiOC), carbon dopedoxide (CDO), organo silicate glass (OSG) spin-on organics, etc.).Although a single ILD 300 is illustrated in FIG. 3, this is onlyexemplary. In some embodiments, multiple ILDs may be used. For example,some regions of the device (e.g., metal layers or portions of metallayers) may use one ILD (e.g., a conventional ILD) and other regions ofthe device may use another ILD (e.g., a low-k ILD). See, for example,commonly-assigned U.S. Patent Application Publication No. 2019/0140019A1, which is incorporated by reference in its entirety herein.

As illustrated in FIG. 3, in some embodiments, a capping layer 310 maybe provided between the different metal layers. Capping layer 310 mayprovide a barrier to migration for the underlying metal layer (e.g.,prevent or reduce copper diffusion) and also act as an etch stop duringfabrication of the overlying structures (e.g., during etching of theoverlying vias). Any material suitable for these functions may be usedas capping layer 310. In some embodiments, capping layer 310 may includematerials, such as, for example, silicon carbide (SiC), silicon nitride(SiN), a nitrogen-doped silicon carbide (e.g., NBLoK from AppliedMaterials, Inc.), etc. IC device 100 may also include a barrier layer320 (or one or more barrier layers), for example, to reduceelectromigration of copper (or another electrical conductive materialused to form the metal structures of device 100). Barrier layer 320 maybe formed of materials, such as, for example, for example, tantalumnitride, tantalum, titanium nitride, titanium-tungsten, tungsten,tungsten nitride, titanium silicon nitride, silicon nitride, cobalt,ruthenium, etc.

As would be recognized by a person skilled in the art, IC device 100 mayalso include additional layers (not shown), such as, for example,transition layers, etch stop layers, barrier layers, etc. See, forexample, U.S. Pat. No. 8,432,035 and U.S. Patent Application PublicationNo. 2014/0065815, which are incorporated by reference in theirentireties herein. Since exemplary materials and structures in an ICdevice, and their functions, are well known in the art, they are notdescribed in detail herein. Further, although a specific configurationof MTJ device 210 and magnetoresistive stack 250 is illustrated in FIG.3, MTJ device 210 may include any type of magnetoresistive device knownin the art, and magnetoresistive stack 250 may be any typemagnetoresistive stack known in the art. In general, MTJ device 210 maybe any type of in-plane or out-of-plane (i.e., perpendicular)magnetically anisotropic MTJ device, and may include any type ofnow-known or later developed magnetoresistive stack 250.

FIGS. 9A-9D depict cross-sectional views of different exemplarymagnetoresistive stacks 250A-250D of an exemplary MTJ device 210 thatmay be used in FIG. 3. In the discussion below, reference will be madeto FIG. 3 and FIGS. 9A-9D. In general, magnetoresistive stack 250 maycomprise at least one fixed magnetic region 60 (or fixed region 60), atleast one free magnetic region 80 (or free region 80), and at least oneintermediate region 70 disposed between the fixed region 60 and the freeregion 80. In some embodiments, magnetoresistive stack 250 may have adual spin filter structure with two intermediate regions 70 as shown inFIG. 9C. The fixed region 60 may be provided below the free region 80(i.e., fixed region 60 proximate bottom electrode 240 and free region 80proximate top electrode 260) as illustrated in FIG. 9B, or the fixedregion 60 may be provided above the free region 80 as shown in FIG. 9A.In some embodiments, fixed region 60 may include one or more layers 62,66 of ferromagnetic alloys (comprising, e.g., some or all of cobalt,iron, nickel, and boron, etc.), and/or free region 80 may comprise oneor more layers 82, 86 of ferromagnetic alloys (comprising e.g., nickel,iron, cobalt, etc.) separated by a antiferromagnetic (AF) coupling layer64, 84 (comprising, e.g., tantalum, tungsten, molybdenum, ruthenium,rhodium, rhenium, iridium, chromium, osmium, etc.). As a person ofordinary skill in the art would recognize, many commonly used layers(e.g., seed layers, transition layers, reference layers, etc.) are notshown in the exemplary stacks of FIGS. 9A-9D for the sake of simplicity.It should be noted that the stacks shown in FIGS. 9A-9D are onlyexemplary and MTJ device 210 may have any now-known or future developedmagnetoresistive stack (including one or more syntheticantiferromagnetic (SAF) structures, synthetic ferromagnetic (SyF)structures, etc.). U.S. Pat. Nos. 8,686,484; 8,747,680; 9,023,216;9,136,464; and 9,419,208, and U.S. Patent Application Publication Nos:2018/0158498; 2019/0165253; 2019/0173004; 2019/0131519; 2019/0140167,and 2019/0157549, each of which is assigned to the assignee of thecurrent application, describe exemplary MTJ devices and exemplarymagnetoresistive stacks that may be used in IC device 100 of FIG. 3.These references are incorporated by reference in their entirety herein.

A method of manufacturing IC device 100 will now be described. Sincedifferent processes (e.g., deposition techniques, etching techniques,polishing techniques, etc.) involved in the manufacturing of IC devicesare well known in the art, detailed description of these techniques isomitted for the sake of brevity. Since MTJ devices 210 of IC device 100are integrated in the MX+1 layer, processing of the metal layers belowand above the MX+1 layer may be performed using conventional ICfabrication processes known in the art. Therefore, for the sake ofbrevity, processing of IC device 100 below the MX+1 layer, and above theMX+1 layer, is not described in detail herein. In some embodiments,during fabrication of IC device 100, processing of memory portion 120may be compartmentalized, such that, before such processing beginsand/or after such processing is complete, a known standard process flowfor IC device 100 may be used. In some embodiments, some of the standardprocess steps and materials may also be used in the compartmentalizedportion of the processing (e.g., the processing used for memory portion120), thereby reducing any additional burden associated with theinclusion of MTJ devices 210 in IC device 100. For example, as explainedpreviously, in the VX layer of FIG. 3, the standard process steps usedto fabricate vias 152 in the logic portion 110 may also be used tofabricate vias 152 in the memory portion 120, thereby simplifying thefabrication process.

FIGS. 4A-4I are a simplified cross-sectional views at different stagesduring an exemplary fabrication process of IC device 100 of FIG. 3. Asexplained above, since conventional processing steps are used tofabricate the device up to the MX layer, these processing steps will notbe described in detail. Briefly, metal patterns, or features,corresponding to the M1 layer are formed (deposited, patterned, etched,etc.) on the back end a semiconductor substrate 300 (see FIG. 3) havingCMOS circuitry. These features may be made of any electricallyconductive material (copper, aluminum, suitable alloys, etc.) and mayinclude any type of feature (such as, for example, a landing pad,conductive trace, etc.) that provides electrical connection to the CMOScircuitry within the die. As is known to a person or ordinary skill inthe art, the features may be formed using known lithographic anddeposition steps. ILD 300 may be deposited over the features of alower-level metal layer, and features and vias may be formed on thedeposited ILD, for example, using a dual-damascene process. For example,with reference to FIG. 4A, ILD 300 may be deposited and patterned usingstandard lithography and etching techniques to form a cavity or a trenchthat, when filled with a conductive material (e.g., copper), will formvias 152 of the VX-1 layer and features 154 of the MX later. Barrierlayer 320 may then be deposited in the trench. Barrier layer 320 mayreduce the migration of copper atoms into ILD 300 and may also providegood adhesion to copper. After deposition of barrier layer 320, a thincopper seed may be deposited (e.g., by physical vapor deposition (PVD))in the trench. This may be followed by the electroplating of copperwhich fills the trench to form vias 152 and features 154. During thisprocess, excess copper may be deposited on the exposed surfaces of ILD300. This excess copper may be removed by a chemical mechanicalpolishing (CMP) process (e.g., copper CMP), and capping layer 310deposited on the polished ILD surface. Different metal and via layersare formed by repeating these process steps for each level ofmetallization.

With reference to FIGS. 4A and 4B, after forming vias 152 of the VX-1layer and features 154 of the MX layer of both the logic and memoryportions 110, 120 (e.g., using the above-described dual-damasceneprocess), ILD 300 is deposited above (or on) capping layer 310. Notethat, in some embodiments, other layers may also be deposited betweencapping layer 310 and ILD 300. Vias 152 of the VX layer are then formedthrough ILD 300 in the memory portion 120 of the device, using, forexample, a single damascene process. For example, ILD 300 above thelogic portion 110 of IC device 100 may be masked (e.g., covered byphotoresist, etc.), and trenches (or cavities in the regions throughwhich vias 152 will pass) are patterned on the ILD 300 in the memoryportion 120. These trenches are then coated with barrier layer 320 andfilled with copper to form vias 152 of the VX layer in memory portion120. The size of the vias 152 formed depend upon the design rules forthe via layer that is being formed. For example, design rules for sometechnology nodes may require the V3 vias to have a width (or diameter)of 32 nm and a height of 53 nm. Therefore, if these design rules arefollowed and vias of the V3 layer are being formed (i.e., if VX of FIG.4B corresponds to V3), then vias 152 of FIG. 4B will be formed to have awidth of 32 nm width and a height of 53 nm. After filling the vias 152,excess copper that is deposited on the surface of ILD 300 is removed by,for example, chemical mechanical polishing (CMP) or another suitableprocess step (e.g., etch-back). The CMP (or etch-back) also planarizesthe surface of the ILD 300 for subsequent processing.

With reference to FIG. 4C, blanket layers of materials that will formdifferent regions of MTJ devices 210 are then sequentially deposited(e.g., deposited one over the other) on the planarized surface of ILD300. These multiple layers include layers 240′, 250′, and 260′ that,after processing, will form the bottom electrode 240, magnetoresistivestack 250, and top electrode 260, respectively, of MTJ device 210 (ofFIG. 3). Any suitable electrically conductive material, such as, forexample, tantalum (Ta), titanium (Ti), tungsten (W), tantalum-nitridealloy, etc. may be used to form bottom and top electrode layers 240′ and260′. The magnetoresistive stack 250 is formed by sequentiallydepositing the different layers of the stack 250 (e.g., the layersdescribed with reference to FIGS. 9A-9D). Since these layers andmaterials that form these layers are known and are described inreferences incorporated by reference herein, they are not discussed indetail. See, for example, commonly-assigned U.S. Patent ApplicationPublication Nos: 2019/0173004; 2017/0125663; 2019/0103554; 2019/0067566,and U.S. Pat. Nos. 8,686,484; 8,747,680; 9,023,216; 9,136,464;9,412,786; 9,419,208; and 9,722,174, each of which is incorporated byreference in its entirety herein.

As shown in FIG. 4C, a hard mask layer 265′ may also be deposited overthe top electrode layer 260′. Hard mask layer 265′ may serve as a hardmask during subsequent processing (etching, patterning, etc.) of themagnetoresistive stack 250 to form MTJ devices 210. For example, hardmask layer 265′ may protect the underlying layers of the stack 250 fromreactive compounds and gases used in the etching processes used to formMTJ devices 210 from magnetoresistive stack 250. In some embodiments,materials such as, for example, silicon oxide, silicon nitride, and/oranother material that is relatively inert to the reactants used duringsubsequent processing, may be deposited to form hard mask layer 265′. Insome embodiments, hard mask layer 265′ may be a metal hard mask, and mayinclude one or more layers of metals, such as, for example, platinum(Pt), iridium (Ir), molybdenum (Mo), tungsten (W), ruthenium (Ru), andalloys, such as, for example, titanium-nitride (TiN), platinum manganese(PtMn), iridium-manganese (IrMn), etc. Some exemplary hard masks aredescribed in commonly-assigned U.S. Patent Application Publication Nos.2015/0079699 A1, and 2014/0190933 A1, which are incorporated byreference in their entireties herein.

As shown in FIG. 4D, the blanket layers of materials (of FIG. 4C) arethen etched for form MTJ devices 210. The formed MTJ devices 210encapsulated with an encapsulating material (or encapsulant 350), andILD 300 deposited over the encapsulated MTJ devices 210. Any now knownetching process (e.g., sputter etching, ion beam etching (IBE) ormilling, reactive ion beam etching (RIE) or milling, etc.) or laterdeveloped etching process may be used to etch through the differentblanket layers to form MTJ devices 210. In some embodiments, a photoresist may be deposited on hard mask layer 265′ and patterned to formhard mask 265 over the desired pattern of MTJ devices 210. Theunderlying layers may then be etched with the patterned hard mask 265serving as a mask to form MTJ devices 210. Since the processing steps(etching, encapsulating, etc.) used to form MTJ devices 210 from blanketlayers are known in the art, they are not described herein. See, forexample, U.S. Patent Application Publication Nos. 2017/0125663 A1 and2019/0173004 A1. After etching, as shown in FIG. 4D, a portion of thehard mask 265 may be retained atop the MTJ devices 210. As also shown inFIG. 4D, due to the isotropic nature of the etching used to form MTJdevices 210, in some embodiments, the formed MTJ devices 210 may havesloping sidewalls (or a frustoconical shape).

After forming the MTJ devices 210, an encapsulating material(encapsulant 350) is deposited on the MTJ devices 210 to form aconformal coating over the exposed regions of the devices 210 (includingtheir side walls). In some embodiments, encapsulant 350 may include anyelectrically nonconductive material, such as, for example, siliconnitride, silicon oxide, aluminum nitride, aluminum oxide, TEOS, etc. Insome embodiments, a conductive material, such as, (e.g., aluminum,magnesium, etc.) may first be deposited and then oxidized or nitridizedto form encapsulant 350. Any suitable process (e.g., chemical vapordeposition (CVD), atomic layer deposition (ALD), etc.) may be used todeposit encapsulant 350. In some embodiments, encapsulant 350 may firstbe deposited over the entire field to cover both the logic portion 110and the memory portion 120, and the deposited encapsulant 350 etchedsuch that only the MTJ devices 210 remain covered by the encapsulant 350(as illustrated in FIG. 4D). ILD 300 is then deposited over theencapsulated MTJ devices 210 to form a conformal coating over both thelogic and memory portions 110, 120. Because of the MTJ devices 210 inmemory portion 120, the surface of the deposited ILD 300 may have anuneven topography (e.g., have peaks and valleys) as illustrated in FIG.4D.

The size of the formed MTJ devices 210 will depend on the metal layer onwhich the devices 210 are formed and the design rules for the technologynode. In some embodiments, when MTJ devices 210 are formed on the M4layer on V3 vias 152 having a width of 32 nm (i.e., when metal layerMX+1 of FIG. 4G is M4), the size (e.g., width, diameter, etc.) of MTJdevices 210 may be about 50 nm. That is, in some embodiments, asillustrated in FIG. 4D, the width of the bottom electrode 240 of MTJdevices 210 may be bigger than via 152 on which the devices 210 areformed. The smaller via below the device 210 reduces (or eliminates insome cases) redeposition of the underlying via material on the sidewalls of MTJ device 210 (or in the space between the devices 210) duringetching of MTJ devices 210. As known to people skilled in the art, theetching processes (such as IBE and RIE that may be used to etch theblanket layers 240′, 250′, 260′ of FIG. 4C) used to form MTJ devices 210use beams of charged ions to etch through the blanket layers 240′, 250′,and 260′. During this etching, the impact of the ions ablates areas ofthe layers not covered by the hard mask 265. A portion of the ablatedmaterial may get redeposited on the side walls of the MTJ devices 210during the etching process. The redeposited material detrimentallyaffects the resistance and magnetic properties of the MTJ devices 210and also may result in electrical shorting of these devices 210. Landingthe MTJ devices 210 on a smaller sized via 152 eliminates (or reduces)the possibility of the material of the via 152 from being ablated andgetting redeposited (on the side walls of the MTJ devices 210 or in thespace between the devices 210) during the etching process.

With reference to FIG. 4E, the surface of ILD 300 is then planarized toremove (or reduce) the unevenness of the ILD topography and prepare thesurface for subsequent processing. In some embodiments, an etch-backprocess may be used to planarize the surface of ILD 300. Any suitableetch-back process known in the art may be used to planarize the surfaceof ILD 300. Typically, the etch-back process used (i.e., etchant,process conditions, etc.) will depend upon the material used as ILD 300.In some embodiments, CF4 gas and/or other etching gases (e.g., composedof C, H, and F) may be used in a RIE process to etch the surface of ILD300. As shown in FIG. 4E, the etch-back process may be stopped beforeexposing the encapsulated MTJ devices 210. Although the surface of theILD 300 is shown to be substantially planar after planarization in FIG.4E, in some embodiments, after etch-back, the surface of ILD 300 in anarea between the logic and memory portions 110, 120 may be uneven (see,for example, FIG. 5D). In some embodiments, instead of an etch-backprocess, a CMP process may be used to planarize the surface of ILD 300.Planarizing the surface of ILD 300 using an etch-back process (ratherthan CMP) may reduce non-uniformity of the surface and/or reduce thepossibility of cross-contamination between the logic and memory portions110, 120.

After planarization of the ILD surface (as shown in FIG. 4E), cavitiesor trenches 154′ and 152′ (corresponding to features 154 of the MX+1layer and vias 152 of the VX layer) are formed on ILD 300 in the logicportion 110 of the device 100 as shown in FIG. 4F. These trenches 154′and 152′ are then filled and polished to form the vias 152 of the VXlayer and the features 154 of the MX+1 layer, as shown in FIG. 4G. Anyprocess known in the art (e.g., a dual damascene process) may be used toform vias 152 and features 154. As explained previously, after formingthe trenches 152′, 154′, barrier layer 320 may first be formed on theside walls of the trenches 152′, 154′, and the trenches 152′, 154′ thenfilled with copper. Filling the trenches 152′, 154′ with copper alsodeposits excess copper on the surface of ILD 300. A polishing step(e.g., copper CMP) may then be performed to remove this excess copperand expose the surface of the features 154. During the polishing, someof the ILD 300 will also be removed to expose a top surface of the MTJdevices 210 in the memory portion 120. See FIG. 4G. Although FIG. 4Gshows a portion of the hard mask 265 above MTJ devices 210 as beingexposed after the polishing, this is only exemplary. In someembodiments, the top electrode 260 (of the MTJ devices 210) may beexposed after the polishing. The portion of MTJ devices 210 that will beexposed may depend upon the selectivity of the encapsulant 350, the ILD300, and/or the material of the top electrode 260 to the polishingprocess used.

After exposing the top surface of the MX+1 metal layer features 154 ofthe logic portion 110, and the top of the MTJ devices 210 of the memoryportion 120, through the surface of ILD 300 (as shown in FIG. 4G),capping layer 310 and ILD 300 is deposited over the exposed surfaces asshown in FIG. 4H. A dual damascene (or another suitable process) is thenbe used to etch trenches 152′ and 154′ through ILD 300 and capping layer310. These trenches 152′ and 154′ are then filled and polished to formthe vias 152 of the VX+1 layer and features 154 of the MX+2 layer asillustrated in FIG. 4I. While etching trench 152′, if the etchant usedin the etching process is selective to the materials of ILD 300 andcapping layer 310, but not selective to the material of encapsulant 350(that covers the side walls of MTJ devices 210), over-etch down thesides of MTJ device 210 can be prevented. That is, if the etchant etchesthe materials of the ILD 300 and capping layer 310 at a faster rate thanit etches encapsulant 350 (if it etches encapsulant 350 at all), thenafter the etching process, the side walls of the MTJ devices 210 willstill be covered by encapsulant 350, thereby preventing deposition ofcopper on the bit side walls during the subsequent via filling process.In some embodiments, to prevent over-etch of the encapsulant 350, ILD300 may first be etched using a first etching process and the cappinglayer 310 may then be etched using a second etching process that isselective to the material of the capping layer 310 (as compared toencapsulant 350).

After exposing the features 154 of the MX+2 layer to form contacts,additional processing may then be carried on IC device 100 (of FIG. 4I)using conventional processing steps to complete the device. That is,additional layers (if any) may be formed, and other processing stepscarried out to prepare IC device 100 for use in any desired application.These steps may include, for example, depositing one or moreencapsulants on the partially formed IC device 100 (of FIG. 4I),polishing the deposited encapsulant to expose conductors connected tothe encapsulated MTJ devices 210 of the memory portion 110 and the logiccircuits of the logic portion 120, and forming a suitable bit contactstructures to electrically connect with the MTJ devices 210 and logiccircuits. Since these processes are well known in the art, they are notdiscussed in more detail herein. See, for example, commonly-assignedU.S. Pat. Nos. 9,548,442, 8,790,935, 8,877,522, 9,711,566, each of whichis incorporated by reference in its entirety herein. It should be notedthat many of the features described above with reference to FIGS. 4A-4Iare exemplary. For example, the materials, structures, and the specificprocessing steps described are only illustrative, and any suitablematerial, structure, and/or processing step known in the art may be usedinstead of those described. For instance, although copper is describedas the material used to fill vias 152 and features 154, any suitableelectrically conductive material known in the art may be used in placeof copper. Further, although a single ILD 300 is described as being usedin all layers, this is also only exemplary. In some embodiments,different ILDs may be used in different layers or in the same layer.

It should also be noted that there may be many variations to the processsteps described above. For example, FIGS. 5A-5H are cross-sectionalillustrations of IC device 100 at different stages of another exemplaryfabrication process. In the process illustrated in FIGS. 5A-5H, in placeof the capping layer 310 uniformly deposited over every metal layer (seeFIG. 3), a metallic capping layer 315 may be selectively deposited (orotherwise formed) over the features 154 formed on each metal layer toserve as a diffusion barrier. See FIG. 5H. Metallic capping layer 315may include any suitable material (such as, for example, cobalt tungstenphosphide or CoWP), and it may be deposited on features 154 by any knownprocess. In the fabrication process of FIGS. 5A-5H, after forming thevias 152 and features 154 of a via layer and a metal layer (e.g.,forming the vias and features using a dual damascene process using, forexample, copper), the metallic capping layer 315 is selectively formedover the features 154. See FIGS. 5A, 5F, and 5H. ILD 300 may then bedeposited on these features and other processing steps carried out in asimilar manner as described with reference to FIGS. 4A-4I. Since theseprocessing steps are similar to those previously described withreference to FIGS. 4A-4I, for the sake of brevity, they are not repeatedagain. It should be noted that the process variation described withreference to FIGS. 5A-5H is only exemplary. Since possible variations inthe fabrication process will be known to a person of ordinary skill inthe art, they are not described herein.

FIG. 6 is a flow chart of an exemplary method 400 used to fabricate anexemplary IC device 100 of the current disclosure. In the discussion ofmethod 400, reference will be made to FIGS. 4A-4I. Since many of theprocessing steps described below have been described previously withreference to FIGS. 4A-4I, they will not be described in detail below. Instep 410, vias 152 and features 154 are formed on ILD 300 using, forexample, a dual damascene process. See FIG. 4A. In step 420, a cappinglayer 310 and ILD 300 are deposited on the features 152 formed in step410. See FIG. 4A. In step 430, vias 152 are formed using, for example, asingle damascene process on ILD 300 deposited over the memory portion120 in step 420. See FIG. 4B. In step 440, MTJ devices 210 are formed onthe vias 152 formed in step 430 in the memory portion 120. See FIGS. 4Cand 4D. In step 450, ILD 300 is deposited to form a conformal coatingover the MTJ devices 210 and over the logic portion 110. See FIG. 4D. Instep 460, vias 152 and features 154 are formed on ILD 300 in the logicportion 110 using, for example, a dual damascene process. See FIGS. 4Fand 4G. In step 470, ILD 300 is again deposited. See FIG. 4H. In step480, vias 152 and features 154 are formed on ILD 300 in both the logicand memory portions 110, 120 using, for example, a dual damasceneprocess to contact the features 154 of the logic portion and the MTJdevices 210 in the memory portion. See FIG. 4I. In step 490, furtherprocessing is carried out using conventional processing techniques tocomplete the IC device.

As alluded to above, the magnetoresistive devices (formed usingaforementioned described techniques and/or processes) may include asensor architecture or a memory architecture (among otherarchitectures). For example, in a magnetoresistive device having amemory configuration, the magnetoresistive devices may be electricallyconnected to an access transistor and configured to couple or connect tovarious conductors, which may carry one or more control signals, asshown in FIG. 7. The magnetoresistive devices may be used in anysuitable application, including, e.g., in a memory configuration. Insuch instances, the magnetoresistive devices may be formed as an ICdevice comprising a discrete memory device (e.g., as shown in FIG. 8A)or an embedded memory device having a logic therein (e.g., as shown inFIG. 8B), each including MRAM, which, in one embodiment isrepresentative of one or more arrays of MRAM having a plurality ofmagnetoresistive devices formed magnetoresistive stacks/structures,according to certain aspects of certain embodiments disclosed herein.

The disclosed process of integrating MTJ devices in a metal layer(rather than in a via layer as is traditionally done (see FIG. 2B)) hasmany advantages. In advanced technology nodes, the lower-layer metals(metal layers closer to the transistors) have scaled down heightrequirements compared to higher-layer metals. For example, in advancedtechnology nodes lower metal layers may have small vertical dimensionsand higher metal layers may have large vertical dimensions. Being ableto integrate MTJ devices in the lower metal layers has advantages forbitcell pitch reduction. Bitcell pitch reduction leads to reduced diearea of IC device 100. A reason for the die area reduction is therelative landing pad area requirements in the different metal layers toenable an integrated MTJ device to be connected to the associatedtransistor. The landing pad area requirement in the higher metal layersmay force a larger pitch. As explained above, traditionally, an MTJdevice was integrated in a IC device (e.g., an MRAM) by providing theMTJ device in the space occupied by a via layer (and in some known ICdevices, in the space occupied by a metal layer and a via layer). In thecurrent disclosure, the MTJ device is provided only in the metal layer.The height of the MTJ device is matched with the height of the metallayer. Higher metal layers tend to have taller rules than the lower vialayers. Therefore, an MVia is not required, reducing the heightrequirement for MTJ integration. Beyond pitch improvement, the currentintegration method has the further advantage of enabling landing the MTJdevice (or MTJ bit) on a smaller standard integration via rather than alarger metal landing pad or utilizing a custom MVia integration. Thesmaller via below the MTJ bit prevents the issue of re-depositingunderlying metal material on to the bit sidewalls or between the bits,which would cause electrical shorts.

In some embodiments, an integrated circuit (IC) device is disclosed. TheIC device includes a logic portion including logic circuits in multiplevertically stacked metal layers interconnected by one or more vialayers, and a memory portion including a plurality of magnetoresistivedevices. Each magnetoresistive device of the plurality ofmagnetoresistive devices may be provided in a single metal layer of themultiple vertically stacked metal layers.

Various embodiments of the disclosed IC device may, alternatively oradditionally, include one or more of the following features: the logicportion may include a first via layer and a second via layer and a firstmetal layer between the first and second via layers, the plurality ofmagnetoresistive devices may be provided in the first metal layer, andvias of both the logic portion and the memory portion in the via layerhave substantially the same configuration; the logic portion may includea first via layer and a second via layer and a first metal layer betweenthe first and second via layers, the plurality of magnetoresistivedevices may be provided in the first metal layer, and vias and metallayers of both the logic portion and the memory portion in the via layermay have substantially the same height; the logic portion may include afirst metal layer, a second metal layer, a third metal layer, a firstvia layer between the first and second metal layers, and a second vialayer between the second and third metal layers, the plurality ofmagnetoresistive devices may be provided in the second metal layer, viasof both the logic portion and the memory portion in the first via layermay have substantially the same configuration, and vias of both thelogic portion and the memory portion in the second via layer may havesubstantially the same configuration; the logic portion includes a firstmetal layer, a second metal layer, a third metal layer, a first vialayer between the first and second metal layers, and a second via layerbetween the second and third metal layers, the plurality ofmagnetoresistive devices may be provided in the second metal layer, viasand metal layers of both the logic portion and the memory portion in thefirst interconnect layer have substantially the same height, and viasand metal layers of both the logic portion and the memory portion in thesecond interconnect layer have substantially the same height; the logicportion may include a first metal layer and a second metal layer and afirst via layer between the first and second metal layers, and theplurality of magnetoresistive devices may be provided in the secondmetal layer such that each magnetoresistive device of the plurality ofmagnetoresistive devices land on vias of the via layer that have asmaller width that the magnetoresistive device; each magnetoresistivedevice of the plurality of magnetoresistive devices may havesubstantially the same thickness as features in the single metal layeron which the plurality of magnetoresistive devices is provided; eachmagnetoresistive device of the plurality of magnetoresistive devices mayhave a single fixed magnetic region separated by a single free magneticregion by an intermediate region; each magnetoresistive device of theplurality of magnetoresistive devices may have a dual spin filterconfiguration; the IC device may further include one more interlayerdielectrics (ILDs) between features of the multiple vertically stackedmetal layers and vias of the one or more via layers.

In some embodiments, a method of fabricating an integrated circuitdevice including a memory portion and a logic portion is disclosed. Themethod may include forming a plurality of first vias on the memoryportion, forming a plurality of magnetoresistive devices in the memoryportion such that each magnetoresistive device of the plurality ofmagnetoresistive devices land on a first via of the plurality of vias,forming a plurality of second vias in the logic portion, and forming aplurality of features in the logic portion such that at least onefeature of the plurality of features land on a second via of theplurality of second vias, and a height of the plurality of plurality offeatures is substantially the same as a height of the plurality ofmagnetoresistive devices.

Various embodiments of the disclosed method may, alternatively oradditionally, include one or more of the following features: the vias ofthe plurality of first vias may have substantially the sameconfiguration as vias of the plurality of second vias; the vias of theplurality of first vias may have substantially the same height as viasof the plurality of second vias; the method may further include forminga plurality of third vias in the logic portion and the memory portion,wherein at least one via of the plurality of third vias land on afeature of the plurality of features in the logic portion, and at leastone via of the plurality of third vias land on a magnetoresistivedevices of the plurality of magnetoresistive devices in the memoryportion; the plurality of second vias in the logic portion and theplurality of features in the logic portion may be formed using a dualdamascene process; the method may further include depositing aninterlayer dielectric (ILD) over the plurality of features in the logicportion and the plurality of magnetoresistive devices in the memoryportion, planarizing a surface of the deposited ILD, and forming aplurality of third vias on the deposited ILD to contact the plurality offeatures and the plurality of magnetoresistive devices.

In some embodiments, an integrated circuit (IC) device is disclosed. TheIC device may include a first metal layer, a second metal layer, and afirst via layer between the first and second metal layers, a logicportion including logic circuits interconnected by the first metallayer, the second metal layer, and the first via layer, and a memoryportion including a plurality of magnetoresistive devices provided inthe second metal layer. A combined height of a magnetically free region,a magnetically fixed region, and an intermediate region positionedbetween the magnetically free region and the magnetically fixed regionof at least one magnetoresistive device of the plurality ofmagnetoresistive devices may be less than or equal to a height of thesecond metal layer.

Various embodiments of the disclosed IC device may, alternatively oradditionally, include one or more of the following features: the firstvia layer may include a plurality of first vias interconnecting thefirst metal layer and the second metal layer in the logic portion andthe memory portion, wherein the first vias in both the logic portion andthe memory portion may have substantially the same height; the IC devicemay include a third metal layer above the second metal layer and asecond via layer between the second and third metal layers, wherein thefirst via layer may include a plurality of first vias interconnectingthe first metal layer and the second metal layer in the logic portionand the memory portion, the second via layer may include a plurality ofsecond vias interconnecting the second metal layer and the third metallayer in the logic portion and the memory portion, the first vias inboth the logic portion and the memory portion may have substantially thesame configuration, and the second vias in both the logic portion andthe memory portion may have substantially the same configuration; the ICdevice may further include a third metal layer above the second metallayer and a second via layer between the second and third metal layers,wherein the first via layer may include a plurality of first viasinterconnecting the first metal layer and the second metal layer in thelogic portion and the memory portion, the second via layer may include aplurality of second vias interconnecting the second metal layer and thethird metal layer in the logic portion and the memory portion, the firstvias in both the logic portion and the memory portion may havesubstantially the same height, and the second vias in both the logicportion and the memory portion may have substantially the same height;and the plurality of magnetoresistive devices may be provided in thesecond metal layer such that each magnetoresistive device lands on viasof the first via layer that have a smaller width that themagnetoresistive device.

Although various embodiments of the present disclosure have beenillustrated and described in detail, it will be readily apparent tothose skilled in the art that various modifications may be made withoutdeparting from the present disclosure or from the scope of the appendedclaims.

1-20. (canceled)
 21. An integrated circuit device comprising: aplurality of vertically stacked metal layers, including a first metallayer and a second metal layer; a plurality of via layers, including afirst via layer between the first metal layer and the second metallayer; a logic portion comprising logic circuits including the firstmetal layer, the second metal layer, and the first via layer; a memoryportion including the first metal layer, the second metal layer, and thefirst via layer; and a plurality of magnetoresistive devices, whereineach magnetoresistive device of the plurality of magnetoresistivedevices is provided in the first metal layer or the second metal layerof the memory portion.
 22. The device of claim 21, wherein a via withinthe logic portion of the first via layer has substantially the sameheight as a via within the memory portion of the first via layer. 23.The device of claim 21, wherein the plurality of via layers furtherincludes a second via layer; the second metal layer is between the firstvia layer and the second via layer; the logic circuits further includethe second via layer; and the memory portion further includes the secondvia layer
 24. The device of claim 23, wherein a combined height of a viawithin the memory portion of the second via layer and a magnetoresistivedevice of the plurality of magnetoresistive devices is substantially thesame as a combined height of a feature of the logic circuits within thesecond metal layer and a via within the logic portion of the second vialayer.
 25. The device of claim 23, wherein a via within the logicportion of the second via layer has substantially the same height as avia within the memory portion of the second via layer.
 26. The device ofclaim 25, wherein each magnetoresistive device of the plurality ofmagnetoresistive devices is provided in the second metal layer of thememory portion.
 27. The device of claim 26, wherein eachmagnetoresistive device of the plurality of magnetoresistive deviceslands on a corresponding via within the memory portion of the first vialayer, and each magnetoresistive device has a width greater than a widthof the corresponding via.
 28. The device of claim 26, wherein amagnetoresistive device of the plurality of magnetoresistive devices hasa height that is substantially the same as a height of a feature of thelogic circuits within the second metal layer.
 29. An integrated circuitdevice comprising: a plurality of vertically stacked metal layers,including a first metal layer; a plurality of via layers, including afirst via layer and a second via layer, wherein the first metal layer isbetween the first via layer and the second via layer; a logic portioncomprising logic circuits including the first metal layer, the first vialayer, and the second via layer; a memory portion including the firstmetal layer, the first via layer, and the second via layer; and aplurality of magnetoresistive devices, wherein each magnetoresistivedevice of the plurality of magnetoresistive devices is within the memoryportion and between the first via layer and the second via layer;wherein a combined height of a magnetically free region, a magneticallyfixed region, and an intermediate region of at least onemagnetoresistive device of the plurality of magnetoresistive devices, isless than or equal to a height of the first metal layer.
 30. The deviceof claim 29, wherein a feature of the logic circuits within the firstmetal layer has a height that is substantially the same as a height ofthe at least one magnetoresistive device of the plurality ofmagnetoresistive devices.
 31. The device of claim 29, further comprisinga second metal layer, wherein the logic circuits further include thesecond metal layer; and vias within the logic portion of the second vialayer, connect the first metal layer to the second metal layer.
 32. Thedevice of claim 31, wherein the memory portion further includes thesecond metal layer; and wherein a height of a via within the memoryportion of the second via layer is substantially the same as a height ofa via within the logic portion of the second via layer.
 33. The deviceof claim 32, further comprising: a third metal layer; and a third vialayer between the first metal layer and the third metal layer; where thelogic circuits further include the third metal layer and the third vialayer; and the memory portion further includes the third metal layer andthe third via layer.
 34. The device of claim 33, wherein a width of theat least one magnetoresistive device is less than a width of a viawithin the memory portion of the third via layer.
 35. The device ofclaim 33, wherein a height of a via within a memory portion of the thirdvia layer is substantially the same as a height of a via within thethird via layer of the logic circuits.
 36. An integrated circuit devicecomprising: a plurality of vertically stacked metal layers, including afirst metal layer; a plurality of via layers, including a first vialayer and a second via layer, wherein the first metal layer is betweenthe first via layer and the second via layer; a logic portion comprisinglogic circuits including the first metal layer, the first via layer, andthe second via layer; a memory portion including the first metal layer,the first via layer, and the second via layer; and a plurality ofmagnetoresistive devices, wherein each magnetoresistive device of theplurality of magnetoresistive devices is provided in the first metallayer; and wherein a via within the logic portion of the first via layerhas substantially the same height as a via within the memory portion ofthe first via layer.
 37. The device of claim 36, wherein a via withinthe logic portion of the second via layer has substantially the sameheight as a via within the memory portion of the second via layer. 38.The device of claim 36, wherein at least one magnetoresistive device ofthe plurality of magnetoresistive devices includes a syntheticantiferromagnetic structure, a synthetic ferromagnetic structure, orboth.
 39. The device of claim 36, wherein a height of the first vialayer is at least about one-third of a height of the first metal layer.40. The device of claim 36, wherein a height of the first metal layer isgreater than a combined height of the first via layer and the second vialayer.